ICS950405 Datasheet, PDF (8/16 Pages) Integrated Circuit Systems – AMD - K8 System Clock Chip

ICS950405
I²C Table: Skew Control Register
Byte 8
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
PCI/HTTSkw3
PCI/HTTSkw2
PCI/HTTSkw1
PCI/HTTSkw0
PCISkw3
PCISkw2
PCISkw1
PCISkw0
Control Function Type
0
1
RW 0000:0 0100:150 1000:300 1100:450
CPU-PCI/HTT 7 Step RW 0001:N/A 0101:N/A 1001:N/A 1101:600
Skew Control (ps) RW 0010:N/A 0110:N/A 1010:N/A 1110:750
RW 0011:N/A 0111:N/A 1011:N/A 1111:900
RW 0000:0 0100:150 1000:300 1100:450
CPU-PCI 7 Step Skew RW 0001:N/A 0101:N/A 1001:N/A 1101:600
Control (ps)
RW 0010:N/A 0110:N/A 1010:N/A 1110:750
RW 0011:N/A 0111:N/A 1011:N/A 1111:900
PWD
1
1
0
0
1
1
0
0
I²C Table: WD Time Control & Async Frequency Selection Register
Byte 9
Pin #
Name
Control Function Type
0
1
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
ASEL
AEN
Reserved
Reserved
WDTCtrl
WD2
WD1
WD0
Async Frequency
Select
RW
66MHz
75.4MHz
AGP/PCI/ Freq Source
Select
RW
FIX PLL
CPU PLL
Reserved
RW
-
-
Reserved
RW
-
-
Watch Dog Time base
Control
RW
290ms Base
1160ms Base
WD Timer Bit 2
RW These bits represent X*290ms (or 1.16S)
WD Timer Bit 1
RW the watchdog timer waits before it goes to
WD Timer Bit 0
RW ^{alarm mode. Default is 7 X 290ms = 2s.}
PWD
0
1
X
X
0
1
1
1
I²C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control Function Type
0
1
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
M/NEN
WDEN
WDStatus
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
M/N Programming
Enable
RW
Disable
Enable
Watchdog Enable RW
Disable
Enable
WD Alarm Status
R
Normal
Alarm
RW
RW
Watch Dog Safe Freq
Programming bits
RW
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
RW
RW
PWD
0
0
0
0
0
0
0
0
I²C Table: VCO Frequency Control Register
Byte 11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
Name
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Control Function Type
0
1
N Divider Prog bit 8 RW The decimal representation of N Divider in
N Divider Prog bit 9 RW
Byte 11 and 12
RW _{The decimal representation of M and N}
RW Divier in Byte 11 and 12 will configure the
M Divider Programming RW VCO frequency. Default at power up =
bits (5:0)
RW
latch-in or Byte 0 Rom table.
RW ^{VCO Frequency = 14.318 x [NDiv(9:0)+8]}
RW
/ [MDiv(5:0)+2]
PWD
X
X
X
X
X
X
X
X
0802F—04/22/05
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