ICS950405 Datasheet, PDF (7/16 Pages) Integrated Circuit Systems – AMD - K8 System Clock Chip

ICS950405
I²C Table: Output Control Register
Byte 4
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
PCIStr1
PCIStr0
PCIStr1
PCIStr0
PCIStr1
PCIStr0
PCIStr1
PCIStr0
Control Function Type
All other PCICLK ^RW
Strength Control RW
PCICLK (7:6) Strength ^RW
Control
RW
PCICLK (5) Strength ^RW
Control
RW
PCICLK (4) Strength ^RW
Control
RW
0
00: 0.5X Drive
01: 1.0X Drive
00: 0.5X Drive
01: 1.0X Drive
00: 0.5X Drive
01: 1.0X Drive
00: 0.5X Drive
01: 1.0X Drive
1
10: 1.5X Drive
11: 2.0X Drive
10: 1.5X Drive
11: 2.0X Drive
10: 1.5X Drive
11: 2.0X Drive
10: 1.5X Drive
11: 2.0X Drive
I²C Table: Reserved Register
Byte 5
Pin #
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I²C Table: Byte Count Register
Byte 6
Pin #
Name
Bit 7
-
BC7
Bit 6
-
BC6
Bit 5
-
BC5
Bit 4
-
BC4
Bit 3
-
BC3
Bit 2
-
BC2
Bit 1
-
BC1
Bit 0
-
BC0
Control Function
Byte Count
Programming b(7:0)
Type
0
1
RW
RW
RW
Writing to this register will configure how
RW _{many bytes will be read back, default is}
RW
06 = 6 bytes.
RW
RW
RW
I²C Table: Byte Count and Vendor ID Register
Byte 7
Pin #
Name
Control Function Type
0
1
Bit 7
-
REV_ID3
RW
-
-
Bit 6
-
REV_ID2
Revision ID
RW
-
-
Bit 5
-
REV_ID1
RW
-
-
Bit 4
-
REV_ID0
RW
-
-
Bit 3
-
Vendor_ID3
RW
-
-
Bit 2
-
Vendor_ID2
Vendor ID
RW
-
-
Bit 1
-
Vendor_ID1
RW
-
-
Bit 0
-
Vendor_ID0
RW
-
-
PWD
0
1
1
1
1
1
1
1
PWD
X
X
X
X
X
X
X
X
PWD
0
0
0
0
0
1
1
0
PWD
0
0
0
0
0
0
0
1
0802F—04/22/05
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