ICS950405 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – AMD - K8 System Clock Chip

ICS950405
Pin Descriptions
PIN # PIN NAME
1 *FS0/REF0
2 VDDHTT
3 X1
4 X2
5 GND
6 *ModeA/HTTCLK0
7 *ModeB/PCICLK8/HTTCLK1
8 PCICLK9/HTTCLK2
9 VDDPCI
10 GND
11 PCICLK11/HTTCLK3
12 PCICLK10
13 PCICLK0
14 PCICLK1
15 GND
16 VDDPCI
17 PCICLK2
18 PCICLK3
19 VDDPCI
20 GND
21 _2XPCICLK4
22 _2XPCICLK5
23 2XPCICLK6
24 2XPCICLK7
25 SCLK
26 SDATA
27 GND
PIN
TYPE
I/O
PWR
IN
OUT
PWR
I/O
I/O
OUT
PWR
PWR
I/O
OUT
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
I/O
PWR
DESCRIPTION
Frequency select latch input pin / 14.318 MHz reference clock.
Supply for HTT clocks, nominal 3.3V.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Mode selection latch input pin / Hyper Transport output.
Mode selection latch input pin / PCI clock output / Hyper Transport output.
PCI clock output / Hyper Transport output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output / Hyper Transport output.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
Clock pin of I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
Ground pin.
28 24_48MHz/Sel24_48#*
I/O 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.
29 AVDD48
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
30 GND
PWR Ground pin.
31 48MHz/FS3**
I/O Fixed 48MHz clock output. 3.3V / 'Frequency select latch input pin
32 PD#*
IN
Asynchronous active low input pin used to power down the device into a low power state.
The internal clocks are disabled and the VCO and the crystal are stopped.
33 GND
PWR Ground pin.
34 GND
PWR Ground pin.
35 VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
36 CPUCLK8C1
OUT Complimentary clock of differential 3.3V push-pull K8 pair.
37 CPUCLK8T1
OUT True clock of differential 3.3V push-pull K8 pair.
38 VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
39 GND
PWR Ground pin.
40 CPUCLK8C0
OUT Complimentary clock of differential 3.3V push-pull K8 pair.
41 CPUCLK8T0
OUT True clock of differential 3.3V push-pull K8 pair.
42 GND
PWR Ground pin.
43 VDDA
PWR 3.3V power for the PLL core.
44 Reset#
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
OUT _{This signal is active low.}
45 REF2/FS2*
I/O 14.318 MHz reference clock / Frequency select latch input pin.
46 VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
47 GND
PWR Ground pin.
48 REF1/FS1*
I/O 14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength
0802F—04/22/05
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