ICS950220 Datasheet, PDF (8/20 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for P4™

Integrated
Circuit
Systems, Inc.
ICS950220
Byte 9: Watchdog Timer Count Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
0
0
0
0
1
0
0
0
Description
The decimal representation of these 8 bits correspond to X •
290ms the watchdog timer will wait before it goes to alarm mode
and reset the frequency to the safe setting. Default at power up is
8 • 290ms = 2.3 seconds.
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Program
Enable
WD Enable
WD Alarm
SF4
SF3
SF2
SF1
SF0
PWD
0
1
1
0
0
0
0
0
Description
Programming Enable bit
0 = no programming. Frequencies are selected by HW latches or Byte0 1
= enable all I²C programing.
Watchdog Enable bit.
This bit will over write WDEN latched value. 0 = disable, 1 = Enable.
Watchdog Alarm Status 0 = normal 1= alarm status
Watchdog safe frequency bits. Writing to these bits will configure the safe
frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
Description
X N divider bit 8
X
X
X _{The decimal respresentation of Mdiv (6:0) corresposd to the}
X reference divider value. Default at power up is equal to the
X ^{latched inputs selection.}
X
X
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
Description
X
X
X _{The decimal representation of Ndiv (8:0) correspond to the}
X _{VCO divider value. Default at power up is equal to the}
X ^{latched inputs selecton. Notice Ndiv 8 is located in Byte 11.}
X
X
X
0467F—07/28/05
8