ICS950220 Datasheet, PDF (2/20 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for P4™

Integrated
Circuit
Systems, Inc.
ICS950220
General Description
The ICS950220 is a single chip clock solution for desktop designs using the Intel 845 chipset with PC133 or DDR memory. It
provides all necessary clock signals for such a system.
The ICS950220 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I²C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
1, 7, 13, 18,
30, 41, 45
2
PIN NAME
VDD
X1
3
4, 8, 14, 19, 25, 29,
32, 36, 42
22, 21, 20
X2
GND
3V66 (3:1)
PCICLK7
5
FS0
PCICLK8
6
FS1
WDEN
9
PCICLK0
17, 16, 15, 12, 11, 10 PCICLK (6:1)
23
RESET#
24
VDDA
Vtt_PWRGD
26
PD#
28
SCLK
27
SDATA
31
3V66_0/24_48MHZ#
FS4
33
AVDD48
48MHz_DOT
34
SEL24_48
35
FS3
48MHz_USB
37
I REF
38
39, 43, 46
MULTSEL0
CPUCLKC (2:0)
40, 44, 47
48
CPUCLKT (2:0)
FS2
REF
0467F—07/28/05
TYPE
DESCRIPTION
PWR 3.3V power supply.
IN Crystal input, has internal load cap (33pF) and feedback resistor from X2.
OUT Crystal output, nominally 14.318MHz. Has internal load cap (33pF).
PWR Ground pins for 3.3V supply.
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
OUT
PWR
IN
IN
IN
I/O
OUT
IN
PWR
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
3.3V Fixed 66MHz clock outputs for HUB.
3.3V PCI clock output
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output.
Logic input frequency select bit. Input latched at power on.
Hardware enable of watch dog circuit. Enabled when latched high.
3.3V PCI clock output.
3.3V PCI clock outputs.
Real time system reset signal for frequency value or watchdog timmer timeout.
This signal is active low.
Analog power 3.3V.
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0)
inputs are valid and are ready to be sampled (active high).
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Clock pin for I²C circuitry 5V tolerant.
Data pin for I²C circuitry 5V tolerant.
3.3V output selectable through I²C to be 66MHz from internal VCO or
48MHz/24MHz.
Logic input frequency select bit. Input latched at power on.
Analog power 3.3V.
3.3V Fixed 48MHz clock output for DOT.
This selects the frequency for the SEL24_48 output.
High = 24MHz, Low = 48MHz.
Logic input frequency select bit. Input latched at power on.
3.3V Fixed 48MHz clock output for USB.
This pin establishes the reference current for the CPUCLK pairs. This pin requires
a fixed precision resistor tied to ground in order to establish the appropriate
current.
3.3V LVTTL input for selecting the current multiplier for CPU outputs
"Complementory" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
Logic input frequency select bit. Input latched at power on.
3.3V, 14.318MHz reference clock output.
2