ICS950220 Datasheet, PDF (6/20 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for P4™

Integrated
Circuit
Systems, Inc.
ICS950220
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Bit7 40, 39
1 CPUT/C2
Bit6 44, 43
1 CPUT/C1
Bit5 47, 46
1 CPUT/C0
Bit4
-
X FS4 Read back
Bit3
-
X FS3 Read back
Bit2
-
X FS2 Read back
Bit1
-
X FS1 Read back
Bit0
-
X FS0 Read back
Description
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Bit7
-
X MULTSEL (Read back)
Bit6
17
1 PCICLK_6
Bit5
16
1 PCICLK_5
Bit4
15
1 PCICLK_4
Bit3
12
1 PCICLK_3
Bit2
11
1 PCICLK_2
Bit1
10
1 PCICLK_1
Bit0
9
1 PCICLK_0
Description
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
Bit7
34
1 48MHZ_DOT
Bit6
35
1 48MHz_USB
Bit5
-
1 Reset gear shift detect 1 = Enable, 0 = Disable
Bit4
-
X Reserved
Bit3
31
0 3V66_0/24_48MHZ#, (default) 1 = 66.66MHz, 0 = 24_48MHZ#
Bit2
-
X Reserved
Bit1
6
1 PCICLK8
Bit0
5
1 PCICLK7
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
Bit 7
-
Async. 3V66 control bit
1 0 : 3V66 / PCI = 64/32 MHz asynchronous with CPU
1 : 3V66 / PCI = 66.6/33.3 MHz synchronous with CPU
Bit 6
-
X Reserved
Bit 5
-
X Reserved
Bit 4
31
1 3V66_0/24_48MHZ#
Bit 3
-
X Reserved
Bit 2
22
1 3V66_3
Bit 1
21
1 3V66_2
Bit 0
20
1 3V66_1
Notes:
1. PWD = Power on Default
2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at
high, CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0467F—07/28/05
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