ICS9248-110 Datasheet, PDF (8/14 Pages) Integrated Circuit Systems – AMD-K7TM System Clock Chip

ICS9248-110
I²C Command Bitmaps
Byte 6: SDRAM Clock & Generator Mode Control Register
Bit
7
3,2, 6:4
1
0
De sc r i pti o n
Spread Spectrum enable (+/- 0.25% center spread) 1=ON 0=OFF
Bit 3
Bit 2
FS2
Bit 6
FS1
Bit 5
FS0
CPU,
Bit 4 SDRAM
PCI
AGP
0
0
0
0
0
90
3 0 .0 0
6 0 .0 0
0
0
0
0
1
95
3 1 .6 7
6 3 .3 3
0
0
0
1
0
100.99 33.66
6 7 .3 3
0
0
0
1
1
115
3 8 .3 3
7 6 .6 7
0
0
1
0
0
1 0 0 .7
3 3 .5 7
6 7 .1 3
0
0
1
0
1
103
3 4 .3 3
6 8 .6 7
0
0
1
1
0
105
3 5 .0 0
7 0 .0 0
0
0
1
1
1
110
3 6 .6 7
7 3 .3 3
0
1
0
0
0
102
3 4 .0 0
6 8 .0 0
0
1
0
0
1
104
3 4 .6 7
6 9 .3 3
0
1
0
1
0
106
3 5 .3 3
7 0 .6 7
0
1
0
1
1
107
3 5 .6 7
7 1 .3 3
0
1
1
0
0
108
3 6 .0 0
7 2 .0 0
0
1
1
0
1
109
3 6 .3 3
7 2 .6 7
0
1
1
1
0
110
3 6 .6 7
7 3 .3 3
0
1
1
1
1
111
3 7 .0 0
7 4 .0 0
1
0
0
0
0
112
3 7 .3 3
7 4 .6 7
1
0
0
0
1
113
3 7 .6 7
7 5 .3 3
1
0
0
1
0
114
3 8 .0 0
7 6 .0 0
1
0
0
1
1
116
3 8 .6 7
7 7 .3 3
1
0
1
0
0
117
3 9 .0 0
7 8 .0 0
1
0
1
0
1
118
3 9 .3 3
7 8 .6 7
1
0
1
1
0
119
3 9 .6 7
7 9 .3 3
1
0
1
1
1
120
3 0 .0 0
6 0 .0 0
1
1
0
0
0
121
3 0 .2 5
6 0 .5 0
1
1
0
0
1
122
3 0 .5 0
6 1 .0 0
1
1
0
1
0
123
3 0 .7 5
6 1 .5 0
1
1
0
1
1
124
3 1 .0 0
6 2 .0 0
1
1
1
0
0
125
3 1 .2 5
6 2 .5 0
1
1
1
0
1
133.33 33.33
6 6 .6 7
1
1
1
1
0
140
3 5 .0 0
7 0 .0 0
1
1
1
1
1
150
3 7 .5 0
7 5 .0 0
0 - Frequency is selected by hardware select, latched input; Spread controlled by pin 29
1 - Frequency is selected by Bit 6:2; Spread controlled by bit 7
0 - SDRAM_OUT Disable
1 - SDRAM_OUT Enable
PWD
0
R eserv ed
Note1
0
1
Notes:
1. Default at power-up will be latched logic inputs to define frequency, as displayed by Bit 1.
2. PWD = Power-Up Default
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