ICS9248-110 Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – AMD-K7TM System Clock Chip

ICS9248-110
Pin Descriptions
PIN NUMBER
2, 1
3
PIN NAME
FS (1:0)
REF (1:0)
GNDREF
4
X1
5
6, 12
X2
GNDPCI
7
PCICLK_F
17, 16, 14, 13, 11, 10, 8
9, 15
18
20, 19
21
34
33
22
23
PCICLK (6:0)
VDDPCI
VDDAGP
AGP (1:0)
GNDAGP
VDD
GND
VDD48
48MHz
24
SEL24-48#
24-48MHz
25
GND48
26
SCLK
27
SDATA
28
FS2
29
SPREAD#
30
PD#
31
CPU_STOP#
32
46
34
35, 44
42, 39, 36
43, 40, 37
38, 41
45
47
48
PCI_STOP#
SDRAM_OUT
VDD
RESERVED
CPUCLKT (2:0)
CPUCLKC (2:0)
GNDCPU
VDDSD
GNDSD
VDDREF
TYPE
IN
OUT
PWR
IN
OUT
PWR
OUT
OUT
PWR
PWR
OUT
PWR
PWR
PWR
PWR
OUT
IN
OUT
PWR
IN
I/O
IN
IN
IN
IN
IN
OUT
PWR
N/C
OUT
OUT
PWR
PWR
PWR
PWR
DESCRIPTION
Frequency Select pins, has pull-up to VDD
14.318MHz clock output
Ground for REF outputs
XTAL_IN 14.318MHz Crystal input, has internal 33pF load
cap and feed back resistor from X2
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output. Not affected by the PCI_STOP#
input.
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Power for AGP outputs, nominally 3.3V
AGP outputs defined as 2X PCI. These may not be stopped.
Ground for AGP clock outputs
Isolated power for core, nominally 3.3V
Isolated ground for core
Power for USB, FDC outputs nominally 3.3V
48MHz output
Selects 24 or 48MHz output for pin 24
Low = 48MHz High = 24MHz
Fixed clock out selectable through SEL24-48#
Ground for 48MHz outputs
Clock input for I²C
Data pin for I²C circuitry 5V tolerant
Frequency Select pin, has pull-up to VDD
Enables Spread Spectrum feature when LOW. Down Spread
0.5% modulation frequency =50KHz
Powers down chip, active low. Internal PLL & all outputs are
disabled.
Halts CPUCLKs. CPUCLKTs driven LOW wheras CPUCLKC
is driven HIGH when this pin is asserted
(Active LOW).
Halts PCI Bus at logic "0" level when driven low. PCICLK_F
is not affected by this pin
Reference clock for SDRAM zero delay buffer
Isolated power for core
Furture CPU power rail
"True" clocks of differential pair CPU outputs. These open
drain outputs need an external 1.5V pull-up.
"Complementory" clocks of differental pair CPU output. These
open drain outputs need an external 1.5V pull_up.
Ground for CPUCLK outputs.
Power for SDRAM_OUT pin. Nominally 3.3V
Ground for SDRAM_OUT pins
Power for REF, X1, X2, nominally 3.3V
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