ICS9248-110 Datasheet, PDF (3/14 Pages) Integrated Circuit Systems – AMD-K7TM System Clock Chip

ICS9248-110
General Description
The ICS9248-110 is a main clock synthesizer chip for AMD-K7 based systems. This provides all clocks required for such a
system when used with a Zero Delay Buffer Chip such as the ICS9179-06.
Spread spectrum may be enabled through I²C programming. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-110
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I²C interface allows changing functions, stop clock programming and frequency selection.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-110. All other clocks will continue to run while the CPUCLKs clocks are
disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width
is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PCI_STOP# (High)
PD# (High)
CPUCLKT
CPUCLKC
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPUCLKs inside the ICS9248-110.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
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