ICS874005 Datasheet, PDF (8/12 Pages) Integrated Circuit Systems – PCI EXPRESS TM JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
3.3V
LVDS_Driv er
3.3V
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS874005 application sche-
matic. In this example, the device is operated at V_DD=3.3V. The
decoupling capacitor should be located as close as possible
to the power pin. The input is driven by a 3.3V LVPECL driver.
VDD = 3.3V
VDDO = 3.3V
R1
10 C3
10uF
C4
0.01u
U1
1
2
3
nQB2
nQA1
4
5
QA1
VDDO
MR
BW_SEL
F_SELA
OEA
6
7
8
9
10
11
12
QA0
nQAO
MR
BW_SEL
VDDA
F_SELA
VDD
OEA
874005_tssop24
Zo = 50 Ohm
Zo = 50 Ohm
24
QB2
VDDO
23
22
QB1
nQB1
21
20
QB0
nQB0
F_SELB
OEB
GND
19
18
17
16
15
GND
nCLK
CLK
14
13
F_SELB
OEB
nCLK
CLK
LVPECL Driv er
(U1:11)
(U1:4) (U1:23)
C5
C6
10uf .1uf
C7
C8
.1uf
.1uf
R4
R5
50
50
R6
50
Zo = 50 Ohm
Zo = 50 Ohm
+
R2
100
-
Zo = 50 Ohm
Zo = 50 Ohm
+
R3
100
-
874005AG
FIGURE 5. ICS874005 SCHEMATIC EXAMPLE
www.icst.com/products/hiperclocks.html
8
REV. A JANUARY 25, 2006