ICS874005 Datasheet, PDF (1/12 Pages) Integrated Circuit Systems – PCI EXPRESS TM JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
GENERAL DESCRIPTION
The ICS874005 is a high performance Diff-
ICS
erential-to-LVDS Jitter Attenuator designed for
HiPerClockS™ _{use in PCI Express systems. In some PCI}
Express systems, such as those found in
desktop PCs, the PCI Express clocks are
generated from a low bandwidth, high phase noise PLL
frequency synthesizer. In these systems, a jitter attenuator
may be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer
and from the system board. The ICS874005 has 3 PLL
bandwidth modes: 200kHz, 400kHz, and 800kHz. The
200kHz mode will provide maximum jitter attenuation, but
with higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated. The 400kHz provides an intermediate bandwidth
that can easily track triangular spread profiles, while
providing good jitter attenuation. The 800kHz bandwidth
provides the best tracking skew and will pass most spread
profiles, but the jitter attenuation will not be as good as the
lower bandwidth modes. Because some 2.5Gb serdes have
x20 multipliers while others have than x25 multipliers, the
874005 can be set for 1:1 mode or 5/4 multiplication mode
(i.e. 100MHz input/125MHz output) using the F_SEL pins.
FEATURES
• Five differential LVDS output pairs
• One differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 30ps (maximum)
• 3.3V operating supply
• 3 bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
PLL BANDWIDTH
The ICS874005 uses ICS 3^rd Generation FemtoClock^TM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package,
making it ideal for use in space constrained applications
such as PCI Express add-in cards.
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~400kHz (Default)
1 = PLL Bandwidth: ~800kHz
BLOCK DIAGRAM
OEA ^Pulldown
F_SELA ^Pulldown
BW_SEL ^Float
0 = ~200kHz
Float = ~400kHz
1 = ~800kHz
CLK ^Pulldown
nCLK ^Pullup
Phase
Detector
VCO
490 - 640MHz
M = ÷5 (fixed)
F_SELA
0 ÷5 (default)
1 ÷4
F_SELB
0 ÷5 (default)
1 ÷4
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
QB2
F_SELB ^Pulldown
MR ^Pulldown
OEB ^Pullup
874005AG
nQB2
www.icst.com/products/hiperclocks.html
1
PIN ASSIGNMENT
nQB2 1
nQA1 2
QA1 3
VDDO 4
QA0 ⁵
nQA0 ⁶
MR ⁷
BW_SEL ⁸
VDDA ⁹
F_SELA ¹⁰
VDD ¹¹
OEA ¹²
24 QB2
2 3 VDDO
22 QB1
21 nQB1
20 QB0
19 nQB0
18 F_SELB
17 OEB
16 _GND
15 _GND
14 _nCLK
13 _CLK
ICS874005
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
REV. A JANUARY 25, 2006