ICS874005 Datasheet, PDF (2/12 Pages) Integrated Circuit Systems – PCI EXPRESS TM JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 24
nQB2, QB2 Output
Differential output pair. LVDS interface levels.
2, 3
nQA1, QA1 Output
Differential output pair. LVDS interface levels.
4, 23
5, 6
V_DDO
QA0, nQA0
Power
Output
Output supply pins.
Differential output pair. LVDS interface levels.
6
nFB_OUT Output
Inverting differential feedback output.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
7
MR
Input
Pulldown
reset causing the true outputs (nQx) to go low and the inverted outputs
(Qx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
8
BW_SEL
Input
Pullup/
Pulldown
PLL Bandwidth input. See Table 3B.
9
V
Power
DDA
Analog supply pin.
10
F_SELA
Input
Pulldown
Frequency select pin for QAx/nQAx outputs.
LVCMOS/LVTTL interface levels.
11
V_DD
Power
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
12
OEA
Input Pullup active. When LOW, the QAx/nQAx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
13
CLK
Input Pulldown Non-inverting differential clock input.
14
nCLK
Input Pullup Inverting differential clock input.
15, 16
17
18
19, 20
GND
OEB
F_SELB
nQB0, QB0
Power
Input
Input
Output
Power supply ground.
Pullup
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
active. When LOW, the QBx/nQBx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
Pulldown
Frequency select pin for QBx/nQBx outputs.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
21, 22
nQB1, QB1 Output
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Inputs
OEA/OEB
0
1
Outputs
QAx/nQAx QBx/nQBx
HiZ
HiZ
Enabled Enabled
TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL
Inputs
PLL_BW
0
1
Float
PLL
Bandwidth
~200kHz
~800kHz
~400kHz
874005AG
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2
REV. A JANUARY 25, 2006