ICS84025 Datasheet, PDF (8/12 Pages) Integrated Circuit Systems – CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
SCHEMATIC EXAMPLE
Figure 4A shows a schematic example of using an ICS84025. In
this example, the input is a 25MHz parallel resonant crystal with
load capacitor CL=18pF. The frequency fine tuning capacitors
C1 and C2 is 22pF and 18pF respectively. This example also
shows logic control input handling. The configuration is set at
F_SEL[1:0]=11 therefore the output frequency is 125MHz. It is
recommended to have one decouple capacitor per power pin.
Each decoupling capacitor should be located as close as pos-
sible to the power pin. The low pass filter R7, C11 and C16 for
clean analog supply should also be located as close to the V
DDA
pin as possible.
VD D
R7
10
C 11
0. 1u
C16
10u
PLL_SEL
VDDA
22p
C1
X1
25MHz, 18pF
C2
18p
F _SEL1
F _SEL0
VD D
U1
13
14
15
16
VDDO
NC
GND
17 ^PLL_SEL
18 ^VDD
19
20
VDDA
GND
21 ^XTAL2
22 ^XTAL1
23
24
MR
F _SEL1
F _SEL0
I CS84025
12
Q5
GN D
Q4
11
10
9
VDDO ₈
Q3 ₇
GN D
Q2
6
5
VDDO ₄
Q1 ₃
GN D
Q0
VDDO
2
1
R6
43
Zo = 50
Zo = 50
R1
43
VDD
RU2
1K
RU3
1K
RU4
1K
SP = Spare, Not Installed
PLL_SEL
F _SEL1
F _SEL0
(U 1, 1)
VD D
(U1,5)
VDD=3.3V
(U1, 9)
(U 1, 13)
(U 1, 17)
RD2
SP
RD3
SP
RD4
SP
C6
0.1u
C5
0. 1u
C3
0.1u
C4
0.1u
C7
0.1u
FIGURE 4A. ICS84025 SCHEMATIC EXAMPLE
84025EM
www.icst.com/products/hiperclocks.html
8
REV. A APRIL 16, 2003