ICS84025 Datasheet, PDF (4/12 Pages) Integrated Circuit Systems – CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS84025
CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TABLE 5A. AC CHARACTERISTICS, V_DD = V_DDA = V_DDO = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_OUT
tjit(cc)
Output Frequency
Cycle-to-Cycle Jitter; NOTE 2
53.125
50
125
MHz
ps
tsk(o) Output Skew; NOTE 1, 2
TBD
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
700
ps
50
%
t_PW
Output Pulse Width
t_PERIOD/2 - TBD
t_PERIOD/2 + TBD ps
t_LOCK
PLL Lock Time
1
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE
5B.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
3.3V
±
5%,
V
DDO
=
2.5V
±
5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_OUT
tjit(cc)
Output Frequency
Cycle-to-Cycle Jitter; NOTE 2
53.125
30
125
MHz
ps
tsk(o) Output Skew; NOTE 1, 2
TBD
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
700
ps
50
%
t_PW
Output Pulse Width
t_PERIOD/2 - TBD
t_PERIOD/2 + TBD ps
t_LOCK
PLL Lock Time
1
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, V_DD = V_DDA = 3.3V ± 5%, V_DDO = 1.8V ± 0.15V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_OUT
tjit(cc)
Output Frequency
Cycle-to-Cycle Jitter; NOTE 2
53.125
30
125
MHz
ps
tsk(o) Output Skew; NOTE 1, 2
TBD
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
700
ps
50
%
t_PW
Output Pulse Width
t_PERIOD/2 - TBD
t_PERIOD/2 + TBD ps
t_LOCK
PLL Lock Time
1
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
84025EM
www.icst.com/products/hiperclocks.html
4
REV. A APRIL 16, 2003