9DBV0641 Datasheet, PDF (8/17 Pages) Integrated Circuit Systems – HCSL compatible differential input; can be driven by common clock sources

9DBV0641 DATASHEET
Electrical Characteristics–Low Power HCSL Outputs
TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Slew rate
Slew rate matching
dV/dt
dV/dt
 dV/dt
Scope averaging on, fast setting
Scope averaging on, slow setting
Slew rate matching, Scope averaging on
1.7 2.9
4 V/ns 1,2,3
1.1 2.1 3.4 V/ns 1,2,3
7
20 % 1,2,4
Voltage High
Voltage Low
V_HIGH
V_LOW
Statistical measurement on single-ended signal _{660 791 850}
7
using oscilloscope math function. (Scope
mV
averaging on)
-150 16 150
7
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Vmax
Vmin
Vswing
Vcross_abs
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
Scope averaging off
800 1150
7
-300 -3
mV
7
300 1548
mV 1,2
250 414 550 mV 1,5
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
13 140 mV 1,6
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured from differential waveform}
3 _{Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around}
differential 0V.
4 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on}
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 _{Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising}
edge (i.e. Clock rising and Clock# falling).
6 _{The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross}
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 _{At default SMBus settings.}
Electrical Characteristics–Current Consumption
TA = T_AMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
I_DDA
VDDA+VDDR, PLL Mode, @100MHz
Operating Supply Current
I_DD
VDD, All outputs active @100MHz
I_DDO
I_DDAPD
VDDIO, All outputs active @100MHz
VDDA+VDDR, CKPWRGD_PD#=0
Powerdown Current
I_DDPD
I_DDOPD
VDD, CKPWRGD_PD#=0
VDDIO, CKPWRGD_PD#=0
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Input clock stopped.}
11
15
6
10
24
30
0.4
0.6
0.5
0.8
0.0003 0.1
UNITS
mA
mA
mA
mA
mA
mA
NOTES
1
1
1
1, 2
1, 2
1, 2
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
8
REVISION B 09/11/14