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9DBV0641 Datasheet, PDF (11/17 Pages) Integrated Circuit Systems – HCSL compatible differential input; can be driven by common clock sources | |||
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9DBV0641 DATASHEET
General SMBus Serial Interface Information
How to Write
⢠Controller (host) sends a start bit
⢠Controller (host) sends the write address
⢠IDT clock will acknowledge
⢠Controller (host) sends the beginning byte location = N
⢠IDT clock will acknowledge
⢠Controller (host) sends the byte count = X
⢠IDT clock will acknowledge
⢠Controller (host) starts sending Byte N through Byte
N+X-1
⢠IDT clock will acknowledge each byte one at a time
⢠Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
IDT (Slave/Receiver)
T
starT bit
Slave Address
WR
WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
O
O
O
Byte N + X - 1
P
stoP bit
ACK
ACK
ACK
ACK
O
O
O
ACK
Note: Read/Write address is latched on SADR pin.
How to Read
⢠Controller (host) will send a start bit
⢠Controller (host) sends the write address
⢠IDT clock will acknowledge
⢠Controller (host) sends the beginning byte location = N
⢠IDT clock will acknowledge
⢠Controller (host) will send a separate start bit
⢠Controller (host) sends the read address
⢠IDT clock will acknowledge
⢠IDT clock will send the data byte count = X
⢠IDT clock sends Byte N+X-1
⢠IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
⢠Controller (host) will need to acknowledge each byte
⢠Controller (host) will send a not acknowledge bit
⢠Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address
WR
WRite
Beginning Byte = N
RT
Repeat starT
Slave Address
RD
ReaD
IDT
ACK
ACK
ACK
ACK
ACK
O
O
O
N
Not acknowledge
P
stoP bit
Data Byte Count=X
Beginning Byte N
O
O
O
Byte N + X - 1
REVISION B 09/11/14
11
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
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