9DBV0641 Datasheet, PDF (4/17 Pages) Integrated Circuit Systems – HCSL compatible differential input; can be driven by common clock sources

9DBV0641 DATASHEET
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1 vSADR_tri
2 ^vHIBW_BYPM_LOBW#
3 FB_DNC
4 FB_DNC#
5 VDDR1.8
6 CLK_IN
7 CLK_IN#
8 GNDDIG
9 SCLK_3.3
10 SDATA_3.3
11 VDDDIG1.8
12 VDDIO
13 vOE0#
14 DIF0
15 DIF0#
16 VDD1.8
17 VDDIO
18 DIF1
19 DIF1#
20 NC
21 vOE1#
22 DIF2
23 DIF2#
24 vOE2#
25 VDDA1.8
26 VDDIO
27 DIF3
28 DIF3#
29 vOE3#
30 NC
31 VDD1.8
32 VDDIO
33 DIF4
34 DIF4#
35 vOE4#
36 DIF5
37 DIF5#
38 vOE5#
39 VDDIO
40 ^CKPWRGD_PD#
41 ePAD
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
LATCHED Trilevel input to select High BW, Bypass or Low BW mode.
IN See PLL Operating Mode Table for Details.
DNC
True clock of differential feedback. The feedback output and feedback input are connected
internally on this pin. Do not connect anything to this pin.
DNC ^{Complement clock of differential feedback. The feedback output and feedback input are}
connected internally on this pin. Do not connect anything to this pin.
1.8V power for differential input clock (receiver). This VDD should be treated as an Analog
PWR _{power rail and filtered appropriately.}
IN True Input for differential reference clock.
IN Complementary Input for differential reference clock.
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 1.8V digital power (dirty power)
PWR Power supply for differential outputs
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
N/A No Connection.
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR 1.8V power for the PLL core.
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
N/A No Connection.
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
IN Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
GND Connect paddle to ground.
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
4
REVISION B 09/11/14