ICS9250-16 Datasheet, PDF (7/17 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

Byte 3: Reserved Register
(1 = enable, 0 = disable)
Bit Pin#
Name
Bit 7 - Reserved
Bit 6 - Reserved
Bit 5 - Reserved
Bit 4 - Reserved
Bit 3 - Reserved
Bit 2 - Reserved
Bit 1 - Reserved
Bit 0 - Reserved
PWD Description
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit Pin#
Name
Bit 7 - Reserved
Bit 6 - Reserved
Bit 5 - Reserved
Bit 4 - Reserved
Bit 3 - Reserved
Bit 2 - Reserved
Bit 1 - Reserved
Bit 0 - Reserved
PWD Description
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
These outputs are designed to be configured at power-on and are not
expected to be configured during the normal modes of operation.
2. PWD = Power on Default
ICS9250-16
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