ICS9250-16 Datasheet, PDF (5/17 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-16
Byte 5: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit
Bit7
Bit6
Bit5
Bit
(3,0)
Bit4
Bit2
Bit1
Desctiption
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
FS2
(HW)
Bit (3,0)
FS0 SEL1
(HW) (Bit3)
CPUCLK SDRAM 3V66
SEL0
MHz
MHz MHz
(Bit0)
0
0
0
0
66.67 100.00 66.60
0
0
0
1
70.00 105.00 70.00
0
0
1
0
72.67 109.00 72.67
0
0
1
1
74.67 112.00 74.66
0
1
0
0
100.00 100.00 66.60
0
1
0
1
105.00 105.00 70.00
0
1
1
0
109.00 109.00 72.67
0
1
1
1
112.01 112.00 74.66
1
0
0
0
133.34 133.34 88.66
1
0
0
1
140.00 105.00 70.00
1
0
1
0
120.00 90.00 60.00
1
0
1
1
124.00 124.00 82.66
1
1
0
0
133.34 100.00 66.60
1
1
0
1
150.00 150.00 75.00
1
1
1
0
140.00 140.00 70.00
1
1
1
1
132.99 132.99 66.60
0 = Down Spread Spread Spectrum 0 to -.5%
1 = Center Spread Spread Spectrum ± .25%
Not used (Needs to be 1 for normal clock operation)
Not used (Needs to be 1 for normal clock operation)
PCICLK
MHz
33.30
35.00
36.33
37.33
33.30
35.00
36.33
37.33
44.33
35.00
30.00
41.33
33.30
37.50
35.00
33.30
PWD
0
0
0
XXXX
Note 1
0
1
1
Note1: Default at power-up will be for Bit 3 and Bit 0 to be 00, with external hardware selection of FS0, FS2
defining specific frequency.
5