ICS9250-16 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-16
General Description
The ICS9250-16 is a single chip clock solution for 810/810E type
chipset. It provides all necessary clock signals for such
a system.
Spread spectrum may be enabled through I²C programming. Spread
spectrum typically reduces EMI by 8dB to 10 dB. This simplifies
EMI qualification without resorting to board design iterations or
costly shielding. The ICS9250-16 employs a proprietary closed
loop design, which tightly controls the percentage of spreading
over process and temperature variations.
Power Groups
VDD0, GND0 = REF & Crystal
VDD1, GND1 = 3V66 (0:1)
VDD2, GND2 = PCICLK(0:7)
VDD3, GND3 = PLL core
VDD4, GND4 = 48MHz (0:1)
VDD5, GND5 = SDRAM_F, SDRAM (0:7)
VDDL0, GNDL0 = CPUCLK (0:2)
VDDL1, GNDL1 = IOAPIC (0:1)
Pin Configuration
PIN NUMBER PIN NAME
FS2
1
REF0
3
X1
4
X2
5, 6, 14, 17, 23,
24, 35, 41, 47
GND (0:5)
8, 7
3V66 [1:0]
2, 9, 10, 21,
22, 27, 33, 38, 44
VDD (0:5)
20,19,18,16,
15,13,12,11
PCICLK[7:0]
25, 26
48MHz (0:1)
28, 29
FS (0:1)
30
SDATA
TYPE
DESCRIPTION
W ^IN
Function Select pin. Determines CPU frequency, all output functionality
(with 50K pull-down).
OUT 3.3V, 14.318MHz reference clock output.
IN
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
OUT
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
PWR Ground pins for 3.3V supply
OUT 3.3V Fixed 66MHz clock outputs for HUB
PWR 3.3V power supply
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
OUT
IN
IN
3.3V Fixed 48MHz clock outputs for USB
Function Select pins. Determines CPU frequency, all output functionality.
Please refer to Functionality table on page 3.
Data input for I²C serial input.
31
SCLK
32
PD#
36, 37, 39, 40,
42, 43, 45, 46
SDRAM [7:0]
34
SDRAM_F
IN Clock input of I²C input
IN
OUT
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
3.3V output running 100MHz. All SDRAM outputs can be turned off
through I²C
OUT 3.3V free running 100MHz SDRAM, cannot be turned off through I²C
56,48
49,50,52
51, 53
54, 55
GNDL [1:0]
CPUCLK [2:0]
VDDL (0:1)
PWR
OUT
PWR
Ground for 2.5V power supply for CPU & APIC
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS (0:2) pins.
2.5V power supply for CPU & IOAPIC
IOAPIC [1:0] OUT 2.5V clock outputs running at 33.3MHz.
2