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| ICS843101I-100 Datasheet, PDF (7/17 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER | |||
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843101I-100
FEMTOCLOCKS⢠CRYSTAL-TO-LVPECL
100MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 8A.
AC
CHARACTERISTICS,
V
CC
=
V
CCA
=
V
CCO
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
fOUT
tjit(Ã)
Output Frequency
RMS Phase Jitter; NOTE 1
Mode = LOW
100MHz, (1.875MHz - 20MHz)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
S_DATA to
tS
Setup Time
S_CLOCK
S_CLOCK
to S_LOAD
10
10
tH
Hold Time
S_DATA to
S_CLOCK
10
NOTE 1: Characterized using a 25MHz crystal.
Typical
100
0.55
475
50
Maximum Units
MHz
ps
ps
%
ns
ns
ns
TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%,VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
fOUT
tjit(Ã)
Output Frequency
RMS Phase Jitter; NOTE 1
Mode = LOW
100MHz, (1.875MHz - 20MHz)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
S_DATA to
tS
Setup Time
S_CLOCK
S_CLOCK
to S_LOAD
10
10
tH
Hold Time
S_DATA to
S_CLOCK
10
NOTE 1: Characterized using a 25MHz crystal.
Typical
100
0.55
442
50
Maximum Units
MHz
ps
ps
%
ns
ns
ns
TABLE 8C. AC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
fOUT
tjit(Ã)
Output Frequency
RMS Phase Jitter; NOTE 1
Mode = LOW
100MHz, (1.875MHz - 20MHz)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
S_DATA to
t
Setup Time S_CLOCK
10
S
S_CLOCK
to S_LOAD
10
tH
Hold Time
S_DATA to
S_CLOCK
10
NOTE 1: Characterized using a 25MHz crystal.
Typical
100
0.55
405
50
Maximum Units
MHz
ps
ps
%
ns
ns
ns
843101AGI-100
www.icst.com/products/hiperclocks.html
7
REV. A OCTOBER 20, 2005
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