ICS843101I-100 Datasheet, PDF (3/17 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843101I-100
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
100MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 2. PIN DESCRIPTIONS
Νυμ βε ρ Ναμ ε
Τψπε
Δ ε σχριπτιον
1, 12
2
V_EE
S_LOAD
Power
Negative supply pins.
Input Pulldown Controls the operation of the Serial input. LVCMOS/LVTTL interface levels.
3
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
4
S_CLOCK
Input
Pulldown
Clock in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
5
SEL
Input
Pulldown
Select pin. When HIGH, selects CLK input.
When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels.
6
OE
Input
Pullup
Output enable pin. Controls enabling and disabling of Q/nQ outputs.
LVCMOS/LVTTL interface levels
7
8
9, 10
V_CCA
V_CC
XTAL_IN,
XTAL_OUT
Power
Power
Input
Analog supply pin.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
11
CLK
Input Pulldown LVCMOS/LVTTL clock input.
13, 14
nQ, Q
Ouput
Differential output pair. LVPECL interface levels.
15
V
Power
CCO
Output supply pin.
16
MODE
Input
Pulldown
MODE pin. LOW = default mode. HIGH = frequency margining mode.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLDOWN
R_PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
843101AGI-100
www.icst.com/products/hiperclocks.html
3
REV. A OCTOBER 20, 2005