ICS843101I-100 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843101I-100
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
100MHZ FREQUENCY MARGINING SYNTHESIZER
FUNCTIONAL DESCRIPTION
The ICS843101I-100 features a fully integrated PLL and
therefore requires no external components for setting the
loop bandwidth. A 24MHz fundamental crystal is used as
the input to the on chip oscillator. The output of the oscilla-
tor is fed into the pre-divider. In frequency margining mode,
the 24MHz crystal frequency is divided by 2 and a 12MHz
reference frequency is applied to the phase detector. The
VCO of the PLL operates over a range of 540MHz to
680MHz. The output of the M divider is also applied to the
phase detector.
The default mode for the ICS843101I-100 is 100MHz output
frequency using a 24MHz crystal. The output frequency
can be changed by placing the device into the margining
mode using the mode pin and using the serial interface to
program the M feedback divider. Frequency margining
mode operation occurs when the MODE input is HIGH. The
phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by an output divider prior to
being sent to the LVPECL output buffer. The divider provides
a 50% output duty cycle. The relationship between the crys-
tal input frequency, the M divider, the VCO frequency and
the output frequency is provided in Table 1. When changing
back from frequency margining mode to nominal mode, the
device will return to the default nominal configuration that
will provide 100MHz output frequency.
Serial operation occurs when S_LOAD is HIGH. Serial data
can be loaded in either the default mode or the frequency
margining mode. The 6-bit shift register is loaded by samp-
ling the S_DATA bits with the rising edge of S_CLOCK.
After shifting in the 6-bit M divider value, S_LOAD is
transitioned from HIGH to LOW which latches the contents
of the shift-register into the M divider control register.
When S_LOAD is LOW, any transitions of S_CLOCK or
S_DATA are ignored.
TABLE 1. FREQUENCY MARGIN FUNCTION TABLE
XTAL Pre-Divider
Reference
Feedback M-Data
(MHz)
(P)
Frequency (MHz) Divider (M) (Binary)
24
2
24
2
24
2
24
2
24
2
24
2
24
2
24
2
24
2
24
2
24
2
12
45
101101
12
46
101110
12
47
101111
12
48
110000
12
49
110001
12
50
110010
12
51
110011
12
52
110100
12
53
110101
12
54
110110
12
55
110111
VCO
(MHz)
540
552
564
576
588
600
612
624
636
648
660
Output
Divider (N)
6
6
6
6
6
6
6
6
6
6
6
Output
Frequency
(MHz)
90
92
94
96
98
100
102
104
106
108
110
% Change
-10.0
-8.0
-6.0
-4.0
-2.0
Nominal Mode
2.0
4.0
6.0
8.0
10.0
SERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
843101AGI-100
M5 M4 M3 M2 M1 M0
tt
SH
t
S
Time
FIGURE 1. SERIAL LOAD OPERATIONS
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2
REV. A OCTOBER 20, 2005