ICS843101I-100 Datasheet, PDF (13/17 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843101I-100
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
100MHZ FREQUENCY MARGINING SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843101I-100.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843101I-100 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core) = V
*I
= 3.465V * 92mA = 318.78mW
MAX
CC_MAX EE_MAX
• Power (outputs)_MAX = 30mW/Loaded Output pair
Total Power_{_MAX} (3.63V, with all outputs switching) = 318.78mW + 30mW = 348.78mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.349W *81.8°C/W = 113.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ_JA FOR 16-PIN TSSOP, FORCED CONVECTION
θ_JA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
137.1°C/W
89.0°C/W
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843101AGI-100
www.icst.com/products/hiperclocks.html
13
REV. A OCTOBER 20, 2005