M1033 Datasheet, PDF (6/14 Pages) Integrated Circuit Systems – VCSO BASED CLOCK PLL WITH AUTOSWITCH

Integrated
Circuit
Systems, Inc.
TriState
The TriState feature puts the LVPECL output driver into
a high impedance state, effectively disconnecting the
driver from the FOUT and nFOUT pins of the device. In
application, the voltage of FOUT and nFOUT will be V_TT,
the LVPECL termination voltage, due to the external
output termination resistors (for LVPECL, this is an
undefined logic condition). The impedance of the clock
net is 50Ω, also due to the external circuit resistors (this
is in distinction to a CMOS output in TriState, which
goes to a high impedance and the logic value floats.)
The 50Ω impedance level of the LVPECL TriState allows
manufacturing In-circuit Test to drive the clock net with
an external 50Ω generator to validate the integrity of
clock net and the clock load.
Any unused output (single-ended or differential) should
be left unconnected (floating) in system application.
This minimizes output switching current and therefore
minimizes noise modulation of the VCSO.
Loss of Reference Indicator (LOR) Output Pin
Each input reference port (DIF_REF0 and DIF_REF1)
has an internal dedicated clock activity monitor circuit.
The output from this circuit for the currently selected
port is provided at device pin LOR, and is also used by
the AutoSwitch circuit when the device is in Auto mode.
The clock activity monitor circuits are clocked by the
PLL phase detector feedback clock. The LOR output is
asserted high if there are three consecutive feedback
clock edges without any reference clock edges (in both
cases, either a negative or positive transition is counted
as an “edge”). The LOR output will otherwise be low.
The activity monitor does not flag excessive reference
transitions in an phase detector observation interval as
an error. The monitor only distinguishes between
transitions occurring and no transitions occurring.
Reference Acknowledgement (REF_ACK) Output
The REF_ACK (reference acknowledgement) pin outputs
the value of the reference clock input that is routed to
the phase detector. Logic 1 indicates input pair 1
(nDIF_REF1, DIF_REF1); logic 0 indicates input pair 0
(nDIF_REF0, DIF_REF0). The REF_ACK indicator is an
LVCMOS output.
M1033/34
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
AutoSwitch (AUTO) Reference Clock Reselection
This device offers an automatic reference clock
reselection feature for switching input reference clocks
upon a reference clock failure. The automatic reference
clock reselection feature, known as AutoSwitch, is
controlled by the device application system through
device pins. When the LOR output is low, the AUTO
input pin can be set high by the system to place the
device into AutoSwitch (automatic reselection) mode.
Once in AutoSwitch mode, when LOR goes high (due to
a fault in the selected reference clock), the input clock
reference is automatically reselected by the internal
AutoSwitch circuit, as indicated by the state change of
the REF_ACK output. Automatic clock reselection is
made only once (it is non-revertive) each time the
AutoSwitch circuit is armed. Re-arming of automatic
mode requires placing the device into Manual Selection
mode (AUTO pin low) before returning to AutoSwitch
mode (AUTO pin high). A more detailed discussion is
provided in the following section.
M1033/34 Datasheet Rev 1.0
6 of 14
Revised 07Apr2005
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