M1033 Datasheet, PDF (1/14 Pages) Integrated Circuit Systems – VCSO BASED CLOCK PLL WITH AUTOSWITCH

Integrated
Circuit
Systems, Inc.
Product Data Sheet
M1033/34
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
The M1033/34 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1033/34 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
FEATURES
◆ Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
◆ Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
◆ LVPECL clock output (CML and LVDS options available)
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Loss of Reference (LOR) output pin; Narrow Bandwidth
control input (NBW pin)
◆ AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
◆ Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
◆ Phase Build-out only upon MUX reselection option
(PBOM)
◆ Pin-selectable feedback and reference divider ratios
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
PIN ASSIGNMENT (9 x 9 mm SMT)
MR_SEL2
MR_SEL0
MR_SEL1
LOR
NBW
VCC
DNC
DNC
DNC
28
18
29
17
30
M1033
16
31
15
32
M1034
14
33
13
34
(Top View)
12
35
11
36
10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1033-11-155.5200 or M1034-11-155.5200
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(Pin Selectable)
(M1033) (M1034)
19.44 or 38.88
77.76
155.52
622.08
(M1033) (M1034)
8 or 4
2
1
0.25
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
M1033/34
Activity
Detector
Activity
Detector
LOR
REF_ACK
REF_SEL
AUTO
4
MR_SEL3:0
2
P_SEL1:0
Auto
Ref Sel
1
0
MUX
0
R Div
1
0
1
M / R Divider
LUT
PLL
Phase
Detector
M Divider
Loop Filter
VCSO
P Divider
(1, 2, or TriState)
TriState
P Divider
LUT
FOUT
nFOUT
Figure 2: Simplified Block Diagram
M1033/34 Datasheet Rev 1.0
Revised 07Apr2005
M1033/34 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel [phone]