ICS95V860 Datasheet, PDF (6/10 Pages) Integrated Circuit Systems – 2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz)

ICS95V8 6 0
Timing Requirements
T_A = 0 - 85°C; Supply Voltage A_VDD, V_DD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Input clock frequency
freq_op
100
225
Input clock duty cycle
d_tin
40
60
UNITS
MHz
%
CLK stabilization
T_STAB
10
µs
Switching Characteristics
T_A = 0 - 85°C; Supply Voltage A_VDD, V_DD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
Low-to high level
propagation delay time
t_PLH1
CLK_IN to any output
High-to low level propagation
delay time
t_PLL1
CLK_IN to any output
Output enable time
t_EN
PD# to any output
Output disable time
t_dis
PD# to any output
Period jitter
T_{jit (per)}
-75
Half-period jitter
t_{(jit_hper)}
-70
Input clock slew rate
t_sl(i)
1
Output clock slew rate
t_sl(o)
1
Cycle to Cycle Jitter¹
T_cyc-T_cyc
-75
Static phase offset
t_spo
-75
Output to Output Skew
T_skew
Duty cycle
D_C2
49
TYP
5.5
5.5
5
5
0
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=t_wH/t_c, where
the cycle (t_c) decreases as the frequency goes up.
MAX UNITS
ns
ns
ns
ns
75
ps
70
ps
4 V/ns
2.5 V/ns
75
ps
75
ps
70
ps
51
%
0675D—01/07/04
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