ICS95V860 Datasheet, PDF (4/10 Pages) Integrated Circuit Systems – 2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz)

ICS95V8 6 0
General Description (Continued)
The ICS95V860 is able to track Spread Spectrum Clock (SSC) for reduced EMI.
The ICS95V860 is an I²C slave/receiver that supports standard and "fast" mode. The ICS95V860 I²C interface is
compliant to "The I2C-Bus Specification", version 2.1 January 2000 Philips Semiconductors, except that I2C_SDA
and I2C_SCL are not 5.0V tolerant, but have a maximum input voltage of 4.2V or V_DDI2C + 0.6V, whichever is
lower. Register bits control the enable for each output pair and a global enable bit (GLOBALEN#) disables all
outputs except the feeback output pair. A low places the disabled output pair in a high impedance state. Outputs
are active during power up and are guaranteed to be at the correct duty cycle and period after the clock
stabilization time.
Device I2C address = 11001, A1, A0, R/W
I²C Table: Output Control Register
Byte 0
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A2,A3
A4,A5
A6,A7
A8,A9
B11,C11
D11,E11
F11,G11
H11,J11
CLK0EN
CLK1EN
CLK2EN
CLK3EN
CLK4EN
CLK5EN
CLK6EN
CLK7EN
Control
Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
I²C Table: Output Control Register
Byte 1
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
L8,L9
L6,L7
L4,L5
L2,L3
H1,J1
-
-
-
CLK8EN
CLK9EN
CLK10EN
CLK11EN
CLK12EN
Reserved
Reserved
GLOBALEN#
Control
Function
Output Control
Output Control
Output Control
Output Control
Output Control
Reserved
Reserved
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
-
-
Enable
1
Enable
Enable
Enable
Enable
Enable
-
-
Disable
PWD
1
1
1
1
1
0
0
0
NOTE: GLOBALEN# does not tristate the feedback output pair. The PLL continues to run and maintains lock even though all other outputs are tri-stated
Disable = Output in high-impedance state
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . . -0.5V to 3.6V
Logic Inputs (except SDA, SCL) . . . . . . . . . GND –0.5 V to V_DD + 0.5 V
Logic Inputs (SDA, SCL) . . . . . . . . . . . . . . . GND –0.5 V to V_DDI2C + 0.6 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
0675D—01/07/04
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