ICS95V860 Datasheet, PDF (3/10 Pages) Integrated Circuit Systems – 2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz)

ICS95V8 6 0
Pin Descriptions
PIN NUMBER
PIN NAME
B3, B4, B7, B8,
C10, D2, D10,
G10, H2, H10, K3,
K4, K7, K8
VDD
A11, B2, B5, B6,
B9, B10, C2, E10,
F10, J2, J10, K2,
K5, K6, K9, K10,
K11, L11
GND
F1
AVDD
F2
L10
A3, A5, A7, A9,
C11, E11, G11,
J11, L2, L4, L6,
L8, H1
A2, A4, A6, A8,
B11, D11, F11,
H11, L3, L5, L7,
L9, J1
AGND
VDD_I2C
CLKT(12:0)
CLKC(12:0)
G2
CLK_INC
G1
CLK_INT
D1
FB_OUTC
C1
E1
E2
A10
A1, B1
K1
L1
FB_OUTT
FB_INT
FB_INC
PD#
I2C_A0, I2C_A1
I2C_SDA
I2C_SCL
TYPE
PWR Power supply 2.5V
DESCRIPTION
PWR Ground
PWR
PWR
PWR
Analog power supply, 2.5V
Analog ground.
I2C VDD pin for I2C_SDA, SCL bias.
OUT "True" Clock of differential pair outputs.
OUT "Complementary" clocks of differential pair outputs.
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
"Complementary" reference clock input
"True" reference clock input
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
Power Down. LVCMOS input
I2C address bits.
I2C bus data line.
I2C bus clock line.
General Description
ICS95V860 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to thirteen
differential clock output pairs (CLKT[0:12], CLKC[0:12]) and one differential clock output feedback pair (FB_OUT,
FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC) the input (PD#) and the Analog Power input (AV_DD).When input (PD#) is low while power is applied, the receivers
are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AV_DD is grounded, the PLL
is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL (appproximately 20MHz), the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low.When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
0675D—01/07/04
(continued)
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