ICS95V860 Datasheet, PDF (1/10 Pages) Integrated Circuit Systems – 2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz)

Integrated
Circuit
Systems, Inc.
ICS95V8 6 0
2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz)
Recommended Application:
DDR Memory Modules / Zero Delay Fan Out Buffer
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 13 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum-tolerant inputs
• Auto PD when input signal removed
• 0°C to 85°C operation
Functionality
INPUTS
AVDD PD# CLK_INT
OUTPUTS
CLK_INC CLKT CLKC FB_OUTT FB_OUTC
PLL State
GND H
L
H
LH
L
H
Bypassed/off
GND H
H
L
HL
H
2.5V
(nom)
L
X
X
Z
Z
Z
2.5V
(nom)
H
L
H
LH
L
2.5V
(nom)
H
H
L
HL
H
2.5V
(nom)
X
<20MHz)
Z
Z
Z
L
Bypassed/off
Z
off
H
on
L
on
Z
off
Switching Characteristics:
• CYCLE - CYCLE jitter (>100MHz):<75ps
• OUTPUT - OUTPUT skew: <70ps
• DUTY CYCLE: 49% - 51%
Block Diagram
PD#
I2C_SCL, I2C_SDA
I2C_A0, I2CA1
Control
Logic
FB_INT
FB_INC
CLK_INC
PLL
CLK_INT
0675D—01/07/04
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
CLKT10
CLKC10
CLKT11
CLKC11
CLKT12
CLKC12