ICS93725 Datasheet, PDF (6/8 Pages) Integrated Circuit Systems – DDR and SDRAM Zero Delay Buffer

ICS9372 5
Switching Characteristics
PARAMETER
Operating Frequency
Input Clock Duty Cycle
DDR Static Phase Error
SDRAM Static Phase Error
SYMBOL
d_in
tped
tpes
DDR output to output Skew
T_skewd
SDRAM output to output Skew
T_skews
DDR Duty Cycle
D_C2
SDRAM Duty Cycle
D_C2
DDR Rise Time
trd
CONDITIONS
Not including FBOUT
to outputs
Not including FBOUT
to outputs
66MHz to 100MHz
101MHz to 200MHz
66MHz to 100MHz
101MHz to 200MHz
Measured between
MIN TYP
66
40
-100 -50
-100 -20
60
200
48
48
48
48
0.55 0.68
DDR Fall Time
tfd
20% and 80% output, CL=16pF 0.63 0.91
SDRAM Rise Time
SDRAM Fall Time
DDR Cycle to Cycle Jitter
trs
tfs
t(_C-C)D
V_OL = 0.4V, V_OH = 2.4V,
CL=30pF
SEL_DDR=1,V_DD=2.5V ,
CL=16pF
0.5 1.4
0.5 1.65
23
SDRAM Cycle to Cycle Jitter
t_(C-C)S
SEL_DDR=0,V_DD=3.3V ,
36
CL=30pF
1_{Guaranteed by design, not 100% tested in production.}
2 _{While the pulse skew is almost constant over frequency, the duty cycle error increases at}
higher frequencies. This is due to the formula: duty cycle=t₂/t₁, where the cycle (t₁) decreases
as the frequency goes up.
Switching Waveforms
Duty Cycle Timing
MAX
200
60
100
100
100
300
52
53
52
56
0.95
1.15
1.7
1.8
38
57
UNITS
MHz
%
ps
ps
ps
ps
%
%
%
%
ns
ns
ns
ns
ps
ps
1.5V
t₁
t₂
1.5V
1.5V
SDRAM Buffer LH and HL Propagation Delay
INPUT
OUTPUT
t₆
0606A—08/01/03
t₇
6