ICS93725 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – DDR and SDRAM Zero Delay Buffer

ICS9372 5
Pin Descriptions
PIN NUMBER
PIN NAME
1, 7, 14, 20 VDD3.3
6, 13, 19, 24, 34,
28, 40
GND
44, 42, 38,
36, 32, 30
DDRT (5:0)
43, 41, 37,
35, 31, 29
DDRC (5:0)
21, 18, 17, 16, 15,
12, 11, 9, 8, 5, SDRAM (12:0)
4, 3, 2
27, 39, 45
VDD2.5
10
BUFFER_IN
22
SDRAMFB_OUT
23
SDFB_IN
25
SDATA
26
SCLK
46
DDRFB_OUT
47
DDRFB_IN
48
SEL_DDR
TYPE
DESCRIPTION
PWR 3.3V voltage supply for SDRAM.
PWR Ground
OUT "True" Clock of differential pair outputs.
OUT "Complementory" clocks of differential pair outputs.
OUT SDRAM clock outputs
PWR 2.5V voltage supply for DDR.
IN Single ended buffer input
OUT Feedback output for SDRAM
IN Feedback input for SDRAM
I/O Data pin for I²C circuitry 5V tolerant
IN Clock input of I²C input, 5V tolerant input
OUT
IN
IN
Feedback output for DDR
Feedback input for DDR
Select input for DDR mode or DDR/SD mode
0=SD mode 1=DDR mode
0606A—08/01/03
2