ICS93725 Datasheet, PDF (1/8 Pages) Integrated Circuit Systems – DDR and SDRAM Zero Delay Buffer

Integrated
Circuit
Systems, Inc.
ICS9372 5
DDR and SDRAM Zero Delay Buffer
Recommended Application:
DDR & SDRAM Zero Delay Buffer for SIS 635/640/645/
650 & 735/740/746 style chipsets.
Product Description/Features:
• Low skew, Zero Delay Buffer
• 1 to 13 SDRAM PC133 clock distribution
• 1 to 6 pairs of DDR clock distribution
• I²C for functional and output control
• Separate feedback path for both memory mode to
adjust synchronization.
• Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs
• Frequency support for up to 200MHz
• Individual I²C clock stop for power mananagement
• CMOS level control signal input
Switching Characteristics:
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time for DDR outputs: 550ps -
1150ps
• DUTY CYCLE: 47% - 53%
Pin Configuration
VDD3.3
1
SDRAM0
2
SDRAM1
3
SDRAM2
4
SDRAM3
5
GND
6
VDD3.3
7
SDRAM4
8
SDRAM5
9
BUFFER_IN
10
SDRAM6
11
SDRAM7
12
GND
13
VDD3.3
14
SDRAM8
15
SDRAM9
16
SDRAM10
17
SDRAM11
18
GND
19
VDD3.3
20
SDRAM12
21
SDFB_OUT
22
SDFB_IN
23
GND
24
48
SEL_DDR*
47
DDRFB_IN
46
DDRFB_OUT
45
VDD2.5
44
DDRT5
43
DDRC5
42
DDRT4
41
DDRC4
40
GND
39
VDD2.5
38
DDRT3
37
DDRC3
36
DDRT2
35
DDRC2
34
GND
33
VDD2.5
32
DDRT1
31
DDRC1
30
DDRT0
29
DDRC0
28
GND
27
VDD2.5
26
SCLK
25
SDATA
48-Pin SSOP
*Internal Pull-up Resistor of 120K to VDD
Block Diagram
BUFFER_IN
SDRAMFB_IN
DDRFB_IN
PLL1
SEL_DDR*
SDATA
SCLK
0606A—08/01/03
Control
Logic
Config.
Reg.
Functionality
SDRAMFB_OUT
DDRFB_OUT
SDRAM (12:0)
3 ^{DDRT (5:0)}
3 ^{DDRCC (5:0)}
MODE
PIN 48
DDR
Mode
DDR/SD
Mode
SEL_DDR=1
SEL_DDR=0
VDD
3.3_2.5
2.5V
3.3V