ICS93725 Datasheet, PDF (3/8 Pages) Integrated Circuit Systems – DDR and SDRAM Zero Delay Buffer

ICS9372 5
Byte 6: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
48
-
-
44, 43
42, 41
38, 37
36, 35
32, 31
PWD
DESCRIPTION
- SEL_DDR (Read back only)
1 (Reserved)
1 (Reserved)
1 DDRT5, DDRC5
1 DDRT4, DDRC4
1 DDRT3, DDRC3
1 DDRT2, DDRC2
1 DDRT1, DDRC1
Byte 7: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
30, 29
21
17, 18
15, 16
11, 12
8, 9
4, 5
2, 3
PWD
DESCRIPTION
1 DDRT0, DDRC0
1 SDRAM12
1
SDRAM10
SDRAM11
1
SDRAM8
SDRAM9
1
SDRAM6
SDRAM7
1
SDRAM4
SDRAM5
1
SDRAM2
SDRAM3
1
SDRAM1
SDRAM0
0606A—08/01/03
3