ICS9250-08 Datasheet, PDF (6/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-08
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
46
49
51
52
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 SDRAM_F (Act/Inact)
1 CPUCLK2 (Act/Inact)
1 CPUCLK1 (Act/Inact)
1 CPUCLK_F (Act/Inact)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
8
16
14
13
12
11
9
PWD
DESCRIPTION
1 Reserved
1 PCICLK_F (Act/Inact)
1 PCICLK5 (Act/Inact)
1 PCICLK4 (Act/Inact)
1 PCICLK3 (Act/Inact)
1 PCICLK2 (Act/Inact)
1 PCICLK1 (Act/Inact)
1 PCICLK0 (Act/Inact)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
30
29
33, 32,
25, 24
22, 21,
19, 18
39, 38,
36, 35
44, 43,
41, 40
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 24MHz (Act/Inact)
1 48MHz (Act/Inact)
1 SDRAM(12:15) (Act/Inact)
1 SDRAM (8:11) (Act/Inact)
1 SDRAM (4:7) (Act/Inact)
1 SDRAM0 (0:3) (Act/Inact)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
X
1
1
X
1
1
X
1
DESCRIPTION
Latched FS0#
Reserved
Reserved
Latched FS1#
Reserved
Reserved
Latched FS3#
Reserved
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
54
55
-
-
2
3
PWD
DESCRIPTION
1 Reserved
X Latched FS2#
1 IOAPIC_F (Act/Inact)
1 IOAPIC0 (Act/Inact)
1 Reserved
1 Reserved
1 REF1 (Act/Inact)
1 REF0 (Act/Inact)
Third party brands and names are the property of their respective owners.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
6