ICS9250-08 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-08
Pin Configuration
PIN NUMBER
2
3
PIN NAME
REF1
FS2¹
REF0
PCI_STOP#¹
4, 10, 23, 26, 34, 42,
48, 53
GND
5
X1
6
X2
PCICLK_F
8
MODE¹
FS3¹
9
PCICLK0
TYPE
OUT
IN
OUT
IN
DESCRIPTION
14.318 MHz reference clock output
Latched frequency select input. Has pull-up to VDDPCI
14.318MHz reference clock output
Halts PCICLK [5:0] at logic "0" level when low.
(in mobile, MODE=0)
PWR Ground.
IN
OUT
OUT
IN
IN
OUT
14.318MHz input. Has internal load cap, (nominal 33pF).
Crystal output. Has internal load cap (33pF) and feedback
resistor to X1
Free running BUS clock not affected by PCI_STOP#
Latched input for MODE select. Converts pin 3 to PCI_STOP# when
low for power management.
Latched frequency select input, pull-down
Free running BUS clock not affected by PCI_STOP#
16, 14, 13, 12, 11 PCICLK [5:1]
OUT PCI Clock Outputs.
17
27
28
30
29
1, 7, 15, 20,
31, 37, 45
24, 25, 32, 33, 18,
19, 21, 22, 35, 36,
38, 39, 40, 41, 43,
44
BUFFERIN
SDATA
SCLK
24MHz
FS0¹
48MHz
FS1¹
VDDPCI, VDDREF,
VDDSDR, VDD48
SDRAM [15:0]
46
SDRAM_F
IN
IN
IN
OUT
IN
OUT
IN
PWR
Input for Buffers
Serial data in for serial config port. (I²C)
Clock input for serial config port. (I²C)
24MHz clock output for Super I/O or FD.
Latched frequency select input. Has pull-up to VDD4.
48MHz clock output for USB.
Latched frequency select input. Has pull-up to VDD2.
Nominal 3.3V power supply, see power groups for function.
OUT SDRAM clocks
OUT Free running SDRAM clock Not affected by CPU_STOP#
47
50, 56
55
51, 49
52
54
CPU_STOP#
VDDLCPU,
VDDLIOAPIC
IOAPIC0
CPUCLK [2:1]
CPUCLK_F
IOAPIC_F
IN
PWR
OUT
OUT
OUT
OUT
Halts CPUCLK [2:1], IOAPIC0, SDRAM [15:0]
clocks at logic "0" level when low.
CPU and IOAPIC clock buffer power supply, 2.5V nominal.
IOAPIC clock output. (14.318 MHz) Poweredby VDDLIOAPIC
CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)
Free running CPU output clock. Not affected ty the CPU_STOP#.
Freerunning IOAPIC clock output. Not affected by the CPU_STOP#
(14.31818 MHz) Powered by VDDLIOAPIC
Notes:
1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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2