ICS9250-08 Datasheet, PDF (14/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-08
General Layout Precautions:
Ferrite
1) Use a ground plane on the top layer
Bead
of the PCB in all areas not used by
VDD
traces.
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
Notes:
1) All clock outputs should have a
series terminating resistor, and a 20pF
capacitor to ground between the
resistor and clock pin. Not shown in
all places to improve readibility of
diagram.
2) Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
C1
C1
2
3.3V Power Route
Component Values:
C1 : Crystal load values determined by user
C2 : 22µF/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 100pF ceramic capacitor
C4 : 20pF capacitor
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0.01µF ceramic
Connections to VDD:
C2
22µF/20V
Tantalum
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
C2
22µF/20V
Tantalum
Ferrite
Bead
VDD
56
C3
55
54
53
52
51
50
C3
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2.5V Power Route
1
Clock Load
3.3V Power Route
Ground
Ground
= Routed Power
= Ground Connection (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
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