ICS86953I-147 Datasheet, PDF (6/13 Pages) Integrated Circuit Systems – DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in
single ended levels. The reference voltage V_REF = V /2 is
DD
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
and R2/R1 = 0.609.
VDD
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
PCLK
nPCLK
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS86953I-147 provides sepa-
rate power supplies to isolate any high switching noise from the
outputs to the internal PLL.V_DDA and V_DDO should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required. Figure 2
illustrates how a 10Ω resistor along with a 10µF and a .01µF
bypass capacitor should be connected to each V_DDA pin.
V_DDO
V_DDA
3.3V
.01µF 10Ω
.01µF
10 µF
FIGURE 2. POWER SUPPLY FILTERING
86953BYI-147
www.icst.com/products/hiperclocks.html
6
REV. B APRIL 23, 2004