ICS86953I-147 Datasheet, PDF (4/13 Pages) Integrated Circuit Systems – DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, V_DDA = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
f
Input Reference Frequency
REF
Maximum Units
175
MHz
TABLE 6. AC CHARACTERISTICS, V_DDA = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
PLL Mode
VCO_SEL = 1
31.25
87.5
f_MAX
Output Frequency PLL Mode
VCO_SEL = 0
62.50
175
Bypass Mode
200
t_PD
Propagation Delay;
NOTE 1
PCLK, nPCLK
2.5
4
tsk(o) Output Skew; NOTE 2, 4
Measured on rising edge
at V_DD/2
75
tjitter(cc) Cycle-to-Cycle Jitter; NOTE 5
50
t(Ø)
Static Phase Offset; NOTE 3, 5
-20
90
200
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
700
47
50
53
t_LOCK
PLL Lock Time
10
t_EN
Output Enable Time; NOTE 4
6
t
Output Disable Time; NOTE 4
7
DIS
NOTE: Termination of 50Ω to V_DD/2.
NOTE 1: Measured from the differential input crossing point to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
MHz
MHz
ns
ps
ps
ps
ps
%
ms
ns
ns
86953BYI-147
www.icst.com/products/hiperclocks.html
4
REV. B APRIL 23, 2004