ICS86953I-147 Datasheet, PDF (5/13 Pages) Integrated Circuit Systems – DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
V_DDA,
V_DDO
LVCMOS
GND
-1.65V±5%
SCOPE
Qx
V_DD
nPCLK
V
PP
PCLK
Cross Points
V
CMR
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
Q0:Q7,
QFB
V
DDO
2
tcycle n
V
DDO
2
➤
tcycle n+1
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
V
DDO
2
Qx
➤
Qy
V
DDO
2
V
DDO
2
t sk(o)
OUTPUT SKEW
20%
Clock
Outputs
80%
t_R
80%
t_F
20%
OUTPUT RISE/FALL TIME
Q0:Q7
QFB
V
DDO
2
Pulse Width
t
PERIOD
odc = ^{t PW}
t _PERIOD
nPCLK
PCLK
Q0:Q7,
QFB
V_DDO
2
t
PD
PROPAGATION DELAY
nPCLK
PCLK
FB_CLK
➤ t(Ø)
V_OH
V_OL
V_OH
V_DDO
2
V_OL
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PHASE JITTER & STATIC PHASE OFFSET
86953BYI-147
www.icst.com/products/hiperclocks.html
5
REV. B APRIL 23, 2004