ICS86953I-147 Datasheet, PDF (13/13 Pages) Integrated Circuit Systems – DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
Rev Table
T1
T2
B
B
T2
Page
2
2
7
8&9
2
REVISION HISTORY SHEET
Description of Change
Added Pullup/Pulldown to Pin 9.
Pin Characteristics table - changed C_IN limit from 4pF max. to 4pF typical.
Added 5pF min. and 7pF typical to C_PD.
Updated Figure 3C and 3D.
Added Layout Guideline and PCB Board layout.
Pin Characteristics Table - added ROUT row.
Date
10/28/03
4/23/04
86953BYI-147
www.icst.com/products/hiperclocks.html
13
REV. B APRIL 23, 2004