ICS83948I Datasheet, PDF (6/10 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in
single ended levels. The reference voltage V_REF = V_DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
and R2/R1 = 0.609.
V_DD
CLK_IN
C1
0.1uF
R1
1K
+
V_REF
-
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
83948AYI
www.icst.com/products/hiperclocks.html
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REV. C DECEMBER 15, 2005