ICS83948I Datasheet, PDF (1/10 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83948I is a low skew, 1-to-12 Differen-
ICS
tial-to-LVCMOS Fanout Buffer and a member
HiPerClockS™ _{of the HiPerClockS™ family of High Performance}
Clock Solutions from ICS. The ICS83948I has
two selectable clock inputs. The CLK, nCLK
pair can accept most standard differential input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS outputs are designed to drive
50Ω series or parallel terminated transmission lines. The
effective fanout can be increased from 12 to 24 by utilizing
the ability of the outputs to drive two series terminated lines.
The ICS83948I is characterized at 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics
make the ICS83948I ideal for those clock distribution ap-
plications demanding well defined performance and re-
peatability.
FEATURES
• Twelve LVCMOS outputs
• Selectable LVCMOS clock or differential CLK, nCLK inputs
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 250MHz
• Output skew: 350ps (maximum)
• Part to part skew: 1.5ns (maximum)
• 3.3V core, 3.3V output
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
CLK_EN
LVCMOS_CLK
1
CLK
nCLK
0
CLK_SEL
D
Q
LE
OE
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
Q0
CLK_SEL 1
LVCMOS_CLK 2
24 GND
23 Q4
Q1
CLK 3
2 2 VDDO
Q2
nCLK 4
ICS83948I ^{21 Q5}
CLK_EN 5
20 GND
Q3
OE 6
19 Q6
Q4
VDD 7
GND 8
1 8 VDDO
17 Q7
Q5
9 10 11 12 13 14 15 16
Q6
Q7
Q8
32-Lead LQFP
Q9
7mm x 7mm x 1.4mm package body
Y Package
Q10
Top View
Q11
83948AYI
www.icst.com/products/hiperclocks.html
1
REV. C DECEMBER 15, 2005