ICS83948I Datasheet, PDF (2/10 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
Clock select input. Selects LVCMOS clock input
1
CLK_SEL
Input Pullup when HIGH. Selects CLK, nCLK inputs when LOW.
LVCMOS / LVTTL interface levels.
2
LVCMOS_CLK
Input Pullup Clock input. LVCMOS / LVTTL interface levels.
3
CLK
Input Pullup Non-inverting differential clock input.
4
nCLK
Input Pulldown Inverting differential clock input.
5
CLK_EN
Input Pullup Clock enable. LVCMOS / LVTTL interface levels.
6
OE
Input Pullup Output enable. LVCMOS / LVTTL interface levels.
7
8, 12, 16,
20, 24, 28, 32
9, 11, 13, 15,
17, 19, 21, 23
25, 27, 29, 31
V_DD
GND
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Power
Power
Output
Positive supply pin.
Power supply ground.
Clock outputs. LVCMOS / LVTTL interface levels.
10, 14, 18, 22, 26, 30
V_DDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
C_IN
C_PD
R_PULLUP
R
PULLDOWN
R_OUT
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum
Typical
4
25
51
51
7
Maximum
Units
pF
pF
kΩ
kΩ
Ω
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
CLK_SEL
0
1
CLK, nCLK
Selected
De-selected
Clock
LVCMOS_CLK
De-selected
Selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
CLK_SEL LVCMOS_CLK
CLK
nCLK
Outputs
Q0:Q12
Input to Output Mode
Polarity
0
—
0
1
LOW Differential to Single Ended Non Inverting
0
—
1
0
HIGH Differential to Single Ended Non Inverting
0
—
0
Biased; NOTE 1 LOW Single Ended to Single Ended Non Inverting
0
—
1
Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inverting
0
—
Biased; NOTE 1
0
HIGH Single Ended to Single Ended Inverting
0
—
Biased; NOTE 1
1
LOW Single Ended to Single Ended Inverting
1
0
—
—
LOW Single Ended to Single Ended Non Inverting
1
1
—
—
HIGH Single Ended to Single Ended Non Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
83948AYI
www.icst.com/products/hiperclocks.html
REV. C DECEMBER 15, 2005
2