ICS83948I Datasheet, PDF (4/10 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS83948I
LOW SKEW, 1-TO-12
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, V_DD = V_DDO = 3.3V±0.3V, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
CLK, nCLK;
NOTE 1A
t_PD
Propagation Delay _{LVCMOS_CLK;}
NOTE 1B
f ≤ 150MHz
f ≤ 150MHz
2.25
2
250
3.75
4
tsk(o) Output Skew; NOTE 2, 6
Measured on
rising edge @V_DDO/2
350
tsk(pp)
Part-to-Part Skew;
NOTE 3, 6
CLK, nCLK
LVCMOS_CLK
Measured on
rising edge @V_DDO/2
1.5
2
t_R
t
F
t_PW
t_PZL, t_PZH
t_PLZ, t_PHZ
t_S
t_H
Output Rise Time
Output Fall Time
Output Pulse Width
Output Disable Time; NOTE 4
Output Enable Time; NOTE 4
Clock Enable
Setup Time;
NOTE 5
Clock Enable
Hold Time;
NOTE 5
CLK_EN to
CLK, nCLK
CLK_EN to
LVCMOS_CLK
CLK, nCLK to
CLK_EN
LVCMOS_CLK
to CLK_EN
0.8V to 2V
0.8V to 2V
f < 150MHz
0.2
0.2
tCycle/2 - 800
1
0
1
1
1.0
1.0
tCycle/2 + 800
11
11
NOTE 1A: Measured from the differential input crossing point to V_DDO/2 of the output.
NOTE 1B: Measured from the V_DD/2 or crosspoint of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ns
ps
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
83948AYI
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4
REV. C DECEMBER 15, 2005