ICS680-01 Datasheet, PDF (6/8 Pages) Integrated Circuit Systems – Networking Clock Synthesizer and Zero Delay Buffer

ICS680-01
Networking Clock Synthesizer and Zero Delay Buffer
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C
Parameter
Symbol
Conditions
Min.
Input Frequency
f_IN
X1
ICLK
Output Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Power-up Time
f_OUT Q0 to Q3, QFB, Note 1
t_OR 20% to 80%, Note 1
t_OF 80% to 20%, Note 1
t_D
at VDD/2, Note 2
40
PLL lock-time from
power-up to 1% of final
frequency
PDTS goes high until
stable CLK outputs at
1% of final frequency
One Sigma Clock Period Jitter
Configuration
dependent
Maximum Absolute Jitter
t_ja
Deviation from mean.
Configuration
dependent.
QFB to ICLK Skew
t_PD Measured at VDD/2,
Note 3
-350
Pin-to-pin Skew
QFB, Q0 to Q3, Note 3 -250
Typ.
25
33
33
1.5
1.5
Max.
60
10
Units
MHz
MHz
MHz
ns
ns
%
ms
2
ms
50
ps
±200
ps
350
250 ps
Note 1: Measured with a 15 pF load.
Note 2: Duty cycle is configuration dependent. Most configurations are min 45% / max 55%.
Note 3: Skew is measured at 1.4 V on rising edges with a 33 MHz ICLK.
MDS 680-01 F
6
Revision 020305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com