ICS680-01 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – Networking Clock Synthesizer and Zero Delay Buffer

ICS680-01
Networking Clock Synthesizer and Zero Delay Buffer
Pin Assignment
X1/ICLK
GND
S0
VDD
CLK1
GND
GND
Q1
Q2
VDD
Q3
Q4
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
24-pin TSSOP
Pin Descriptions
X2
VDD
PDTS
S1
25M
ICLK
VDD
QFB
VDD
48M
CLK2
GND
Output Clock Select Table
S0 S1 CLK1 (MHz) CLK2 (MHz)
MM
OFF
48
00
50
48
01
66.6666
48
10
50
24
11
66.6666
24
Pin
Number
1
2
3
4
5
Pin
Name
X1/ICLK
GND
S0
VDD
CLK1
6
GND
7
GND
8
Q1
9
Q2
10
VDD
11
Q3
12
Q4
13
GND
14
CLK2
15
48M
16
VDD
17
QFB
Pin
Type
XI
Power
Input
Power
Output
Power
Power
Output
Output
Power
Output
Output
Power
Output
Output
Power
Output
Pin Description
Crystal input. Connect this pin to a crystal or external clock source.
Connect to ground.
Select pin 0. See table above.
Connect to voltage supply.
Selectable output clock. See table above. Weak internal pull-down when
tri-state.
Connect to ground.
Connect to ground.
Clock output 1. Weak internal pull-down when tri-state.
Clock output 2. Weak internal pull-down when tri-state.
Connect to voltage supply.
Clock output 3. Weak internal pull-down when tri-state.
Clock output 4. Weak internal pull-down when tri-state.
Connect to ground.
Selectable output clock. See table above. Weak internal pull-down when
tri-state.
48 MHz output clock. Weak internal pull-down when tri-state.
Connect to voltage supply.
Feedback pin. Internally connected.
MDS 680-01 F
2
Revision 020305
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