ICS680-01 Datasheet, PDF (1/8 Pages) Integrated Circuit Systems – Networking Clock Synthesizer and Zero Delay Buffer

ICS680-01
Networking Clock Synthesizer and Zero Delay Buffer
Description
Features
The ICS680-01 generates four high-frequency clock
outputs and a reference from a 25 MHz crystal or clock
input. The device includes a low-skew, single input to
four output zero delay clock buffer. It can replace
multiple crystals and oscillators, saving board space
and cost.
The device has a power-down tri-state (PDTS) pin that
place the clock outputs in a high-impedance state when
pulled low. The PDTS pin includes an internal pull-up
resistor.
Block Diagram
• Packaged in 24-pin TSSOP
• Available in Pb (lead) free package
• Replaces multiple crystals and oscillators
• Input crystal or clock frequency of 25 MHz
• Five output driver driven by external clock
• Duty cycle of 45/55
• Operating voltage of 3.3 V
• Advanced, low-power CMOS process
• Fixed output frequencies of 25 MHz and 48 MHz
• Selectable output frequencies of 24 MHz, 48 MHz,
50 MHz and 66.6666 MHz
• Qx outputs replace costly discrete buffer
• Low-skew buffer outputs (250 ps)
VDD
5
S0
S1
25 MHz
Crystal or Clock
X1/ICLK
X2
External capacitors
may be required.
PLLA
PLLB
PLLC
Crystal
Oscillator
Divide
Logic
and
Output
Enable
Control
CLK1
CLK2
48M
25M
QFB
Q0
ICLK
PLL/Buffer
2
GND
Q1
Q2
Q3
PDTS
MDS 680-01 F
1
Revision 020305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com