ICS9DB108 Datasheet, PDF (5/15 Pages) Integrated Circuit Systems – Eight Output Differential Buffer for PCI-Express

Integrated
Circuit
Systems, Inc.
ICS9DB108
Absolute Max
Symbol
Parameter
VDD_A
VDD_In
V_IL
V_IH
Ts
Tambient
Tcase
ESD prot
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND-0.5
-65
0
2000
Max
4.6
4.6
V_DD+0.5V
150
70
115
Units
V
V
V
V
°_C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V_IH
3.3 V +/-5%
2
V_IL
3.3 V +/-5%
GND - 0.3
I_IH
V_IN = V_DD
-5
I_IL1
V_IN = 0 V; Inputs with no pull-up
-5
resistors
I_IL2
V_IN = 0 V; Inputs with pull-up
resistors
-200
MAX
V_DD + 0.3
0.8
5
UNITS NOTES
V
V
uA
uA
uA
Operating Supply Current I_DD3.3OP
Full Active, C_L = Full load;
250
mA
Powerdown Current
I_DD3.3PD
all diff pairs driven
all differential pairs tri-stated
60
mA
12
mA
Input Frequency³
F_i
V_DD = 3.3 V
80
100/133
166/200
220
MHz
3
Pin Inductance¹
L_pin
7
nH
1
Input Capacitance¹
C_IN
C_OUT
Logic Inputs
Output pin capacitance
1.5
5
pF
1
6
pF
1
PLL Bandwidth when
PLL Bandwidth
BW
PLL_BW=0
PLL Bandwidth when
PLL_BW=1
4
MHz 1
2
MHz 1
Clk Stabilization^1,2
T_STAB
From V_DD Power-Up and after
input clock stabilization or de-
1
ms 1,2
assertion of PD# to 1st clock
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Tdrive_SRC_STOP#
DIF output enable after
SRC_Stop# de-assertion
10
ns 1,3
Tdrive_PD#
DIF output enable after
PD# de-assertion
300
us 1,3
Tfall
Fall time of PD# and
SRC_STOP#
5
ns
1
Trise
Rise time of PD# and
SRC_STOP#
5
ns
2
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3_{Time from deassertion until outputs are >200 mV}
0723D—01/08/04
5