ICS9DB108 Datasheet, PDF (3/15 Pages) Integrated Circuit Systems – Eight Output Differential Buffer for PCI-Express

Integrated
Circuit
Systems, Inc.
ICS9DB108
Pin Description (Continued)
PIN # PIN NAME
25 GND
26 PD#
27 SRC_STOP#
28 HIGH_BW#
29 DIF_4#
30 DIF_4
31 VDD
32 GND
33 DIF_5#
34 DIF_5
35 OE_5
36 OE_6
37 DIF_6#
38 DIF_6
39 VDD
40 GND
41 DIF_7#
42 DIF_7
43 OE_4
44 OE_7
45 LOCK
46 IREF
47 GNDA
48 VDDA
PIN TYPE
DESCRIPTION
PWR
IN
IN
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
IN
PWR
PWR
Ground pin.
Asynchronous active low input pin used to power down the
device. The internal clocks are disabled and the VCO and the
crystal are stopped.
Active low input to stop diff outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
3.3V output indicating PLL Lock Status. This pin goes high when
lock is achieved.
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
0723D—01/08/04
3